Design and Simulation of Logic Circuits at Nano Scale Beyond 32 Nano Meters (FinFet) (International Journal of Innovative Research in Engineering & Management, 2023)
With advancement in electronic circuitry,  efforts are made to minimize chip size and to attain the  desired performance so on changing one parameter the  other parameters are effected like variables of field effect  transistor like length and width are key variables available  to the circuit designer to optimize circuit performance  .When in FET’s like CMOS (complementary metal oxide  semiconductor) the dimensions are decreased, the short  channel effect arises and creates a problem of concern.  With this effect an exponential increase in the leakage  current happens. In order to reduce the SCE and hence  leakage current, a new technology came into being in  recent years in which a 3D multiple gate CMOS like FinFet  (Fin Field Effect Transistor) has been developed which  possess advantages over conventional FET’s and has  attracted many engineers and designers to make it more  sophisticated. This technology works in the nano meter  range to minimize short channel effects. Many companies  like Intel, advanced micro device, global foundries have  started using FinFet technology. I have carried out my  work on the basis of current researches on FinFet  technology and how FinFet technology can be used in  future to design new logic and memory devices like  Inverter, MUX etc. Various  parameters of FinFet like reduced short channel effects,  less leakage current, low power consumption, less  propagation delay and less time delay are discussed.  Various mathematical models and software were used to  simulate power, delay, power delay product, average  power dissipation and energy delay products, this  technology was designed to  eliminate the problem of SCE by permitting transistors to  be scaled down into sub 20nm range. Use of PMT model  to design different logic devices at 16nm technology and  analyzed output of each circuit. Parameters like Power  dissipation, time delay and PDP were compared between  MOSFET (CMOS) technology and FinFet technology for  each circuit.
Keywords: CMOS; Logic Circuits; FinFet; Short Channel Effect; VLSI