2:1 Multiplexer Design Using Lector, LCnmos, LCpmos Power Reduction Techniques with 45nm, 90nm, 180nm CMOS Technology (International Journal of Innovative Research in Computer Science & Technology, 2022)
Today’s modern communication requires  high data transmission rate and low power consumption.  One of the most common concept of data transmission can  be achieved by Multiplexers. The Multiplexers are the logic  designs where data can be transmitted by n number of  inputs over transmission path based on the selection line  producing the single input. The application of Multipis more active in communications system. AlsoLow power consumption and high-speed result is the major concern for  choosing the digital circuits [1,2]. Here we designed 2:1 Multiplexer using CMOS technology  with 45nm, 90nm, 180nm. Since CMOS offers less power  consumption, we can till reduce the power consumed by  using power reduction techniques. In this paper we  designed and compared the 2:1 Multiplexer using Lector,  LCnmos and LCpmos power reduction techniques.
Keywords: Multiplexer; CMOS technology; Lector technique; LCnmos technique and LCpmos technique